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3.1.7.1
Self-Test Control (ST_X, ST_Y)
The ST_X and ST_Y bits enable and disable the self-test circuitry for their respective axes. Self-Test circuitry is enabled if a
logic ’1’ is written to ST_X, or ST_Y and the ENDINIT bit has not been set. Enabling the self-test circuitry results in a positive
acceleration value on the enabled axis. Self-test deflection values are specified in Section 2.4 . ST_X and ST_Y are always
cleared following internal reset.
When the self-test circuitry is active, the offset cancellation block and the offset monitor status are suspended, and the status
bits in the Acceleration Data Request Response will indicate ”Self-Test Active”. Reference Section 3.8.4 and Section 4.2 for de-
tails. When the self-test circuitry is disabled by clearing the ST_X or ST_Y bit, the offset monitor remains disabled until the time
t ST_OMB , specified in Section 2.5 , expires. However, the status bits in the Acceleration Data Request Response will immediately
indicate that self-test has been deactivated.
3.1.7.2
Reserved Bits (Reserved)
Bits 6 through 4 of the DEVCFG_X and DEVCFG_Y registers are reserved. A write to the reserved bits must always be logic
’0’ for normal device operation and performance.
3.1.7.3
Low-Pass Filter Selection Bits (LPF_X[3:0], LPF_Y[3:0])
The Low Pass Filter selection bits independently select a low-pass filter for each axis as shown in Table 11 . Refer to Section
3.8.3 for details regarding filter configurations.
Table 11. Low Pass Filter Selection Bits
LPF_X[3] /
LPF_Y[3]
LPF_X[2] /
LPF_Y[2]
LPF_X[1] /
LPF_Y[1]
LPF_X[0] /
LPF_Y[0]
Low Pass Filter Selected Nominal Sample Rate ( μ s)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100 Hz, 4 pole
300 Hz, 4 Pole
400 Hz, 4 Pole
800 Hz, 4 Pole
1000 Hz, 4 pole
400 Hz, 3 Pole
Reserved
Reserved
50 Hz, 4 pole
150 Hz, 4 Pole
200 Hz, 4 Pole
400 Hz, 4 Pole
500 Hz, 4 Pole
200 Hz, 3 Pole
Reserved
Reserved
8
8
8
8
8
8
Reserved
Reserved
16
16
16
16
16
16
Reserved
Reserved
Note: Filter characteristics do not include g-cell frequency
response.
3.1.8
Arming Configuration Registers (ARMCFGX, ARMCFGY)
The arming configuration registers contain configuration information for the arming function. The values in these registers are
only relevant if the arming function is operating in moving average mode, or count mode.
These registers can be written during initialization but are locked once the ENDINIT bit is set. Refer to Section 3.1.6.2 . These
registers are included in the writable register CRC check. Refer to Section 3.2.2 for details.
Table 12. Arming Configuration Register
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$0E
$0F
ARMCFGX
ARMCFGY
Reserved
Reserved
Reserved
Reserved
APS_X[1]
APS_Y[1]
APS_X[0]
APS_Y[0]
AWS_XN[1] AWS_XN[0]
AWS_YN[1] AWS_YN[0]
AWS_XP[1]
AWS_YP[1]
AWS_XP[0]
AWS_YP[0]
Reset Value
0
0
0
0
1
1
1
1
MMA68xx
Sensors
16
Freescale Semiconductor, Inc.
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